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Method and system of high-availability PCIE SSD with software-hardware jointly assisted implementation to enhance immunity on multi-cell upset
Method and system of high-availability PCIE SSD with software-hardware jointly assisted implementation to enhance immunity on multi-cell upset
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机译:具有软件-硬件联合辅助实施的高可用性PCIE SSD的方法和系统,以增强对多小区干扰的抵抗力
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摘要
It is detected that an error has occurred on an FPGA while the FPGA is operating in a first mode, wherein the error is not correctable by the FPGA itself. The FPGA is configurable to operate in the first mode in which a set of processing steps is to be performed by a first set of logic cells within the FPGA, or in a second mode in which at least a portion of the set of processing steps is to be performed outside the FPGA enabled by a second set of logic cells within the FPGA. An error location associated with the error is identified. In the event that the error location is deemed to have occurred in a critical subset of the first set of logic cells: the FPGA is switched to operate in the second mode; at least one of the first set of logic cells is reconfigured; and upon successful reconfiguration, the FPGA is switched to operate in the first mode.
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