Test and training enabling architecture gateway implemented on a chip

摘要

Disclosed herein is a specialized integrated circuit for a Test and Training Enabling Architecture (TENA) gateway. The specialized integrated circuit comprises a packet parser, a TCP packet handler, generic TENA packet generator(s), and object model specific TENA packet generator(s). The packet parser parses an incoming MAC layer packet and conditionally provides a TCP packet to the TCP packet handier, depending on header(s) in the MAC layer packet. The TCP packet handler parses the TCP packet to reveal a TENA message, and determines whether the TENA message involves object model specific data and selectively provides the TENA message to the generic TENA packet generator(s) or to the object model specific TENA packet generator(s). The selection is based on the object model specific data determination. The selected TENA packet generator constructs an outgoing TENA message in response to the provided TENA message.