instruction and logic for performing a double word / saturated quadruple vector addition

摘要

instruction and logic for performing a double word / quadruple saturated vector addition In many embodiments, vector extensions to an instruction set architecture include instructions for making both unsigned and unsaturated integer additions saturated. In one embodiment, a vector-sign saturated integer addition is provided. in one embodiment, an unsigned integer addition with unsigned saturation vector is provided. In one embodiment, packaged double word and quadruple word integers are supported for both signed and unsigned instructions.