Inhibitor system for hardware attacks on a l2c bus, slave module and network that includes it (Machine-translation by Google Translate, not legally binding)

摘要

A hardware attack inhibiting system for a slave module (20) in an i2c bus including detector (42) for detecting the start of communication in the sda data line and for generating an initialization signal; an oscillator (44) for generating an independent clock signal; a meter (46) for automatically measuring the frequency of the synchronization signal scl and for comparing it with the clock signal of the oscillator (44) and for generating a signal indicating the existence of an attack; a response device (48) configured to receive the signal indicating the existence of an attack and to regenerate the scl line from the signal of the oscillator device (44). (Machine-translation by Google Translate, not legally binding)