Inhibitor system hardware attacks in a L2C bus, slave Module and network that includes

摘要

The invention relates to a system for preventing hardware attacks for a slave module (20) in an I2C bus, which system includes: a detector (42) for detecting the initiation of communication in a data line, SDA, and generating an initialisation signal; an oscillator (44) for generating an independent clock signal; a meter (46) for automatically measuring the frequency of a synchronisation signal, SCL, comparing same to the clock signal of the oscillator (44), and generating a signal indicating the existence of an attack; a response device (48) configured to receive the signal indicating the existence of an attack and to regenerate the SCL line from the signal of the oscillator (44).