A processor (20) includes a pipeline (28, 32, 36, 44, 52) and control circuitry (60, 64, 68). The pipeline is configured to process instructions of program code and includes one or more fetch units (28). The control circuitry is configured to predict at run-time one or more future flow-control traces to be traversed in the program code, to define, based on the predicted flow-control traces, two or more regions of the program code from which instructions are to be fetched, wherein the number of regions is greater than the number of fetch units, and to instruct the pipeline to fetch instructions alternately from the two or more regions of the program code using the one or more fetch units, and to process the fetched instructions.
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