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HARDWARE NODE WITH MATRIX-VECTOR MULTIPLY TILES FOR NEURAL NETWORK PROCESSING
HARDWARE NODE WITH MATRIX-VECTOR MULTIPLY TILES FOR NEURAL NETWORK PROCESSING
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机译:带矩阵向量的硬件节点神经网络处理
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摘要
Hardware and methods for neural network processing are provided. A method in a system comprising a plurality of nodes, where each node comprises a plurality of tiles, is provided. The method includes receiving an N by M matrix of coefficients configured to control a neural network model. The method includes storing a first row and a second row of the N by M matrix of coefficients in a first and a second on-chip memories incorporated within a first and a second of the plurality of tiles. The method includes processing the first row of the coefficients and a first set of input vectors using a first compute unit incorporated within the first of the plurality of tiles. The method includes processing the second row of the coefficients and a second set of input vectors using a second compute unit incorporated within the second of the plurality of tiles.
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