III-V SEMICONDUCTOR STRUCTURE HAVING COLUMN III-V ISOLATION REGIONS

摘要

dielectric; A non-column III-V doped semiconductor layer disposed on the dielectric; And an insulating barrier comprising a column III-V material disposed vertically through the semiconductor layer to the dielectric. In one embodiment, the semiconductor layer is silicon and has CMOS transistors disposed in the semiconductor layer above a first region of the dielectric and a III-V transistor disposed over another region of the dielectric. The barrier electrically isolates the column III-V transistor from the CMOS transistors. In one embodiment, the structure includes a passive element disposed over the semiconductor layer and a plurality of laterally spaced III-V structures, wherein the III-V structures are disposed under the passive element, the III- V structures pass vertically through the semiconductor layer to the insulating layer.