PARALLEL PROCESSING UNIT COMPUTING DEVICE INCLUDING THE SAME AND THREAD GROUP SCHEDULING METHOD

摘要

The present invention provides a parallel processing unit capable of reducing cache interference without dropping a thread level parallelism, a computing device including the same and a warp scheduling method. In the parallel processing unit including a multiprocessor, the multiprocessor comprises a memory unit which includes a level 1 data (L1D) cache and a sharing memory to which a plurality of cache lines are allocated. A thread group scheduler isolates a second thread group by changing a cache access of the second thread group into the sharing memory, when a first thread group of an active state satisfies a predetermined first condition.