Adaptive Peripheral Component Interconnects for Optimal Performance and Power Savings

摘要

Systems, methods, and apparatus for adaptively modifying latency times that govern entry into low power states of a PCIe interface are described. The method performed by the controller of the PCIe interface comprises determining that a burst of data is being transmitted on the PCIe link, configuring a timer to signal when an entry latency period has elapsed after determining that the PCIe link has entered the idle state Causing the one or more circuits of the PCIe interface to enter a low-power state when the timer signals that an entry latency period has elapsed before a PCIe link is activated, and causing the one or more circuits of the PCIe interface to enter a low- Increasing the entry latency period if the number of entries of the PCIe interface into the power state exceeds the threshold maximum number of times.