III-N GROUP III-N TRANSISTORS ON NANOSCALE TEMPLATE STRUCTURES

摘要

III-N semiconductor channel is formed on the III-N transition layer formed on the (111) or (110) surface of the silicon template structure such as a pin sidewall. In embodiments, the silicon pin allows for more compliant gajyeoseo a width comparable with the III-N epitaxial layer thickness for the seeding layer, a lower density of defects and / or epitaxial film reduction in thickness. In embodiments, the transition layer is GaN and the semiconductor channel comprising indium (In) in order to increase the conduction band offset from the silicon pin. In other embodiments, the pin is then removed or, if oxidized, or other sacrificial there is converted to a dielectric structure for transistor fabrication. In certain embodiments employing a sacrificial pin, III-N transition layer and the semiconductor channel is a substantially pure GaN then allow a higher breakdown voltage than could be capable of supporting the presence of the silicon pin.;