2 2-Step time to digital converter based all digital delay-locked loop and method for controlling the same

摘要

The present invention relates to a two-step time-to-digital converter-based fully digital delay locked loop circuit and a control method thereof wherein the two-step time-to-digital converter-based fully digital delay locked loop circuit has a fast locking time and performance of lower power and a smaller chip area. The two-step time-to-digital converter-based fully digital delay locked loop circuit comprises: a digital control delay line which changes a phase between an input clock signal (CLKIN) and an output clock signal (CLKOUT) and finally reduces phase errors between the CLKIN and a DQ clock signal (CLKDQ); a replica clock buffer which receives input of the CLKOUT, output from the digital control delay line, and makes a phase of a feedback clock signal (CLKFB) and a phase of the CLKDQ the same by outputting the CLKFB delayed by a predetermined time; a two-step time-to-digital converter which searches for a coarse lock point and a fine lock point and generates a code for removing error to reduce the phase difference between the CLKFB and the CLKIN; and a shift register which receives input of a coarse delay code and a fine delay code, which are output by the two-step time-to-digital converter, stores a code in accordance with a control signal of a shift register controller, and applies the code to a digital control delay line.