Energy-efficient processor core architecture for image processors

摘要

A device will be described. The device includes a program controller for retrieving and issuing commands. The device comprises an execution track with at least one execution unit for executing the instructions. The execution lane is part of an execution lane matrix coupled to a two-dimensional shift register matrix structure, wherein the execution lanes of the execution lane matrix are located at respective matrix positions and coupled to dedicated registers at the same respective matrix positions in the two-dimensional shift register matrix.