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Energy-efficient multicore processor architecture for parallel processing
Energy-efficient multicore processor architecture for parallel processing
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机译:高效的多核处理器架构,可进行并行处理
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摘要
A multicore computer architecture provides for clock dividers on each core, the clock dividers capable of providing rapid changes in the clock frequency of the core. The clock dividers are used to reduce the clock frequency of individual cores spinning while waiting for a synchronization instruction resolution such as a lock variable. Core power demands may be decreased before and after change in dock speed to reduce power bus disruption.
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