Dual Target Type Conversion, Mixed Precision Accumulation and Mixed Precision Atomic Memory Operations

摘要

Disclosed embodiments relate to dual target type conversion, accumulation, and atomic storage instruction instructions. In one example, a system includes a memory, a processor, including: a fetch circuit for fetching the instruction from a code store, the instruction including an opcode, a first destination identifier, and a source identifier for specifying a source vector register, the source vector register having a plurality of single source codes. Precision floating point data elements include a decode circuit for decoding the fetched instruction, and an execution circuit for executing the decoded instruction to: convert the elements of the source vector register to double precision floating point values, storing a first half of the double precision floating point values at a first location which is identified by the first destination identifier and storing a second half of the double-precision floating-point values at a second location.