The floating point number is the most commonly used real number representation for digital computations due to its high precision characteristics. It is used on computers and on single chip applications such as DSP chips. double precision (64-bit) representations allow for a wider range of real numbers to be denoted. However, single precision (32-bit) operations are more efficient. Recently, there has been an increasing interest in mixed precision computations which take advantage of single precision efficiency on 64-bit numbers. This calls for the ability to interchange between the two formats. In this paper, an algorithm that converts floating point numbers from 64- to 32-bit representations is presented. The algorithm was implemented as a verilog code and tested on field programmable gate array (FPGA) using the Quartus II DE2 board and Agilent 16821A portable logic analyzer. Results indicate that the algorithm can perform the conversion reliably and accurately within a constant execution time of 25 ns with a 20 MHz clock frequency regardless of the number being converted.
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机译：浮点数由于其高精度特性而成为数字计算中最常用的实数表示。它用于计算机和单芯片应用程序，例如DSP芯片。双精度（64位）表示允许表示更大范围的实数。但是，单精度（32位）操作效率更高。最近，人们对混合精度计算越来越感兴趣，这种计算利用了64位数字的单精度效率。这要求能够在两种格式之间互换。本文提出了一种将浮点数从64位表示转换为32位表示的算法。该算法被实现为Verilog代码，并使用Quartus II DE2板和Agilent 16821A便携式逻辑分析仪在现场可编程门阵列（FPGA）上进行了测试。结果表明，该算法可以在25 ns的恒定执行时间内以20 MHz的时钟频率可靠，准确地执行转换，而与转换的数量无关。
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