首页> 外国专利> The neural optimization circuit, the architecture and method for the arrays of neurons.

The neural optimization circuit, the architecture and method for the arrays of neurons.

机译:神经优化电路,神经元阵列的结构和方法。

摘要

A neuron circuit is capable of producing a weighted sum of digitized input signals and applying an activation function to the weighted sum so as to produce a digitized activation signal as output. The circuit includes at least: one multiplier multiplying each input signal (x1 to xn) with a weight value (w1j to wnj), one accumulator accumulating the results of the multiplier so as to produce the weighted sum, and one activation unit executing the activation function. The activation unit comprises at least one shift unit and at least one saturation unit capable of approximating a non-linear activation function. The result of the approximated activation function is obtained by one or more arithmetic shifts applied to the weighted sum.
机译:神经元电路能够产生数字化的输入信号的加权和并将激活函数应用于加权和,从而产生数字化的激活信号作为输出。该电路至少包括:一个乘法器,将每个输入信号(x1至xn)与权重值(w1j至wnj)相乘;一个累加器,累加该乘法器的结果以产生加权和;以及一个激活单元,执行激活功能。激活单元包括至少一个移位单元和至少一个能够近似非线性激活函数的饱和单元。近似激活函数的结果是通过对加权和应用一个或多个算术移位获得的。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号