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BINARY NEURAL NETWORKS ON PROGAMMABLE INTEGRATED CIRCUITS

机译:可编程集成电路上的二进制神经网络。

摘要

In an example, a circuit of a neural network implemented in an integrated circuit (IC) includes a layer of hardware neurons, the layer including a plurality of inputs, a plurality of outputs, a plurality of weights, and a plurality of threshold values, each of the hardware neurons including: a logic circuit having inputs that receive first logic signals from at least a portion of the plurality of inputs and outputs that supply second logic signals corresponding to an exclusive NOR (XNOR) of the first logic signals and at least a portion of the plurality of weights; a counter circuit having inputs that receive the second logic signals and an output that supplies a count signal indicative of the number of the second logic signals having a predefined logic state; and a compare circuit having an input that receives the count signal and an output that supplies a logic signal having a logic state indicative of a comparison between the count signal and a threshold value of the plurality of threshold values; wherein the logic signal output by the compare circuit of each of the hardware neurons is provided as a respective one of the plurality of outputs.
机译:在示例中,以集成电路(IC)实现的神经网络的电路包括硬件神经元层,该层包括多个输入,多个输出,多个权重和多个阈值,每个硬件神经元包括:逻辑电路,其输入从多个输入的至少一部分接收第一逻辑信号,并且输出提供与第一逻辑信号的异或(XNOR)相对应的第二逻辑信号,以及至少多个配重的一部分;计数器电路,其具有接收第二逻辑信号的输入和提供计数信号的输出,该计数信号表示具有预定逻辑状态的第二逻辑信号的数量;比较电路,其输入端接收计数信号,输出端提供逻辑信号,该逻辑信号具有表示计数信号与多个阈值中的阈值之间的比较的逻辑状态。其中,由每个硬件神经元的比较电路输出的逻辑信号被提供为多个输出中的相应一个。

著录项

  • 公开/公告号EP3494521A1

    专利类型

  • 公开/公告日2019-06-12

    原文格式PDF

  • 申请/专利权人 XILINX INC.;

    申请/专利号EP20170749012

  • 发明设计人 UMUROGLU YAMAN;BLOTT MICHAELA;

    申请日2017-07-24

  • 分类号G06N3/063;

  • 国家 EP

  • 入库时间 2022-08-21 12:29:35

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