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CLOCK TREE IMPLEMENTATION METHOD, SYSTEM-ON-CHIP AND COMPUTER STORAGE MEDIUM

机译:时钟树实现方法,片上系统和计算机存储介质

摘要

A clock tree implementation method, system-on-chip and computer storage medium, being applied to the system-on-chip comprising a core module (10) and an externally connected module (20); an interconnection matrix (12) in the core module (10) is connected to the externally connected module (20) by a bus converting bridge (11) comprising a protocol bridge (111) and a frequency dropping bridge (112); converting a data bus into a first configuration bus (S100) through the protocol bridge (111), the frequency of the first configuration being the frequency of the protocol bridge; converting the first configuration bus into a second configuration bus (S101) through the frequency dropping bridge (112), the frequency of the second configuration bus being the frequency of the configuration bus of the externally connected module.
机译:一种时钟树的实现方法,系统级芯片和计算机存储介质,应用于包括核心模块(10)和外部连接模块(20)的系统级芯片。核心模块(10)中的互连矩阵(12)通过总线转换桥(11)连接到外部连接的模块(20),所述总线转换桥包括协议桥(111)和降频桥(112)。通过协议桥(111)将数据总线转换为第一配置总线(S100),第一配置的频率为协议桥的频率;通过所述降频桥(112)将所述第一配置总线转换为第二配置总线(S101),所述第二配置总线的频率为所述外部连接模块的配置总线的频率。

著录项

  • 公开/公告号EP3173895B1

    专利类型

  • 公开/公告日2018-11-28

    原文格式PDF

  • 申请/专利权人 SANECHIPS TECHNOLOGY CO. LTD.;

    申请/专利号EP20140881692

  • 发明设计人 ZHANG QING;LI JIAN;LIU GUISHENG;

    申请日2014-12-25

  • 分类号G06F1/12;G06F1/10;G06F13/42;G06F15/78;G06F1/08;

  • 国家 EP

  • 入库时间 2022-08-21 12:27:44

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