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Semiconductor memory device with a control logic capable of controlling the ready busy output control unit to adjust an output current to be outputted to a ready/busy pad, and a method for operating the same
Semiconductor memory device with a control logic capable of controlling the ready busy output control unit to adjust an output current to be outputted to a ready/busy pad, and a method for operating the same
A semiconductor memory device includes a memory cell array, a status signal generator, an RB output control unit and a control logic. The memory cell array includes a plurality of memory cells. The status signal generator outputs an internal status signal indicating whether the memory cell array is performing an internal operation. The RB output control unit outputs a ready/busy signal based on the internal status signal. The control logic controls the RB output control unit to adjust an output current of the RB output control unit.
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