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Variable loop gain using excessive regeneration for a delayed wide-area control system

机译:对于延迟的广域控制系统,使用过度再生的可变环路增益

摘要

Disclosed are methods and systems for adjusting a High Voltage Direct Current (HVDC) compensator output signal to an HVDC system to reduce control loop modulus due to excessive time delay of sensor measurements. Two different time windows, a Short-Time Variance Window (STVW) and an Extended-Time Variance Window (ETVW) may be examined for detection of increased energy. To detect increased energy the HVDC compensator output signal may be passed through a bandpass filter, then variances for the STVW and ETVW may be generated to produce corresponding test statistics. The STVW and ETVW test statistics may be compared to hypothesis test thresholds and have binary logic based on the hypothesis test comparisons used to generate a gain. The gain may then be multiplied times the original HVDC feedback compensator output such that the adjusted HVDC feedback compensator output reduces the control loop modulus when applied to the HVDC system.
机译:公开了用于将高压直流(HVDC)补偿器输出信号调节到HVDC系统以减小由于传感器测量的过度时间延迟而导致的控制回路模量的方法和系统。可以检查两个不同的时间窗口,即短时方差窗口(STVW)和扩展时方差窗口(ETVW),以检测增加的能量。为了检测增加的能量,可以使HVDC补偿器输出信号通过带通滤波器,然后可以生成STVW和ETVW的方差以产生相应的测试统计量。可以将STVW和ETVW测试统计数据与假设测试阈值进行比较,并基于用于生成增益的假设测试比较具有二进制逻辑。然后可以将增益乘以原始的HVDC反馈补偿器输出,以使调整后的HVDC反馈补偿器输出在应用于HVDC系统时降低控制环路模量。

著录项

  • 公开/公告号US10355485B2

    专利类型

  • 公开/公告日2019-07-16

    原文格式PDF

  • 申请/专利权人 UNIVERSITY OF WYOMING;

    申请/专利号US201815959039

  • 发明设计人 DAKOTA ROBERSON;JOHN F. OBRIEN;

    申请日2018-04-20

  • 分类号H02J3;H02J3/18;H02J3/36;G01R35/02;

  • 国家 US

  • 入库时间 2022-08-21 12:16:23

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