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Maskless epitaxial growth of phosphorus-doped Si and boron-doped SiGe (Ge) for advanced source/drain contact

机译:用于高级源极/漏极接触的磷掺杂硅和硼掺杂硅锗(Ge)的无掩模外延生长

摘要

A method is presented for forming a transistor having reduced parasitic contact resistance. The method includes forming a first device over a semiconductor structure, forming a second device adjacent the first device, forming an ILD over the first and second devices, and forming recesses within the ILD to expose the source/drain regions of the first device and the source/drain regions of the second device. The method further includes forming a first dielectric layer over the ILD and the top surfaces of the source/drain regions of the first and second devices, a chemical interaction between the first dielectric layer and the source/drain regions of the second device resulting in second dielectric layers formed over the source/drain regions of the second device, and forming an epitaxial layer over the source/drain regions of the first device after removing remaining portions of the first dielectric layer.
机译:提出了一种用于形成具有减小的寄生接触电阻的晶体管的方法。该方法包括:在半导体结构上形成第一器件;在第一器件附近形成第二器件;在第一和第二器件上方形成ILD;以及在ILD内形成凹槽以暴露第一器件和源极/漏极的源极/漏极区。第二器件的源/漏区。该方法进一步包括在ILD以及第一和第二器件的源/漏区的顶表面上方形成第一介电层,第一介电层和第二器件的源/漏区之间的化学相互作用导致第二。在第二器件的源/漏区上方形成电介质层,并在去除第一电介质层的剩余部分之后在第一器件的源/漏区上方形成外延层。

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