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Feed forward equalizer with power-optimized distributed arithmetic architecture and method

机译:具有功率优化的分布式算术架构的前馈均衡器和方法

摘要

A distributed arithmetic feed forward equalizer (DAFFE) and method. The DAFFE includes look-up tables (LUTs) in offset binary format. A DA LUT stores sum of partial products values and an adjustment LUT stores adjustment values. DA LUT addresses are formed from same-position bits from all but the most significant bits (MSBs) of a set of digital words of taps and an adjustment LUT address is formed using the MSBs. Sum of partial products values and an adjustment value are acquired from the DA LUT and the adjustment LUT using the DA LUT addresses and the adjustment LUT address, respectively. Reduced complexity downstream adder(s) (which result in reduced power consumption) compute a total sum of the sum of partial products values and the adjustment value (which compensates for using the offset binary format and dropping of the MSBs when forming the DA LUT addresses) to correctly solve a DA equation.
机译:分布式算术前馈均衡器(DAFFE)和方法。 DAFFE包含偏移二进制格式的查找表(LUT)。 DA LUT存储部分产品值的总和,而调整LUT存储调整值。 DA LUT地址由抽头数字字集的除最高有效位(MSB)以外的所有位置相同的位形成,并使用MSB形成调整LUT地址。使用DA LUT地址和调整LUT地址分别从DA LUT和调整LUT获取部分乘积值和调整值。降低复杂度的下游加法器(可降低功耗)计算部分乘积值和调整值的总和(补偿使用偏移二进制格式和形成DA LUT地址时MSB的丢失) )正确求解DA方程。

著录项

  • 公开/公告号US10432436B1

    专利类型

  • 公开/公告日2019-10-01

    原文格式PDF

  • 申请/专利权人 GLOBALFOUNDRIES INC.;

    申请/专利号US201816216248

  • 申请日2018-12-11

  • 分类号G06F1/3203;H04L25/03;H03M7/42;H03K19/177;H04L27/01;

  • 国家 US

  • 入库时间 2022-08-21 12:15:37

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