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Feed forward equalizer with power-optimized distributed arithmetic architecture and method

摘要

A distributed arithmetic feed forward equalizer (DAFFE) and method. The DAFFE includes look-up tables (LUTs) in offset binary format. A DA LUT stores sum of partial products values and an adjustment LUT stores adjustment values. DA LUT addresses are formed from same-position bits from all but the most significant bits (MSBs) of a set of digital words of taps and an adjustment LUT address is formed using the MSBs. Sum of partial products values and an adjustment value are acquired from the DA LUT and the adjustment LUT using the DA LUT addresses and the adjustment LUT address, respectively. Reduced complexity downstream adder(s) (which result in reduced power consumption) compute a total sum of the sum of partial products values and the adjustment value (which compensates for using the offset binary format and dropping of the MSBs when forming the DA LUT addresses) to correctly solve a DA equation.

著录项

  • 公开/公告号US10721104B2

    专利类型

  • 公开/公告日2020.07.21

    原文格式PDF

  • 申请/专利权人

    申请/专利号US16525723

  • 申请日2019.07.30

  • 分类号

  • 国家 US

  • 入库时间 2022-08-21 10:58:22

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