首页> 外国专利> Mechanism to provide back-to-back testing of memory controller operation

Mechanism to provide back-to-back testing of memory controller operation

机译:提供对内存控制器操作的背对背测试的机制

摘要

Embodiments are generally directed to a mechanism to provide back-to-back testing of memory controller operation. An embodiment of an apparatus includes a test controller including a specialized self-testing mechanism for memory control testing, the memory control testing including testing with back-to-back transactions; and a memory controller, the memory controller including one or more transaction arbiters, one or more arbiter queues for memory transactions, an auto response mechanism to provide a response to a read transaction, and a switching mechanism to switch the memory control between a functional mode and an auto response mode. The test controller is to generate test transactions and transfer the test transactions to the memory controller. The memory controller is to block the one or more transaction arbiters, place the plurality of test transactions in the one or more arbiter queues, and to unblock the transaction arbiters upon an event.
机译:实施例大体上针对提供对存储器控制器操作的背对背测试的机制。装置的实施例包括测试控制器,该测试控制器包括用于存储器控制测试的专用自测试机制,该存储器控制测试包括具有背对背事务的测试;存储器控制器,该存储器控制器包括一个或多个事务仲裁器,用于存储器事务的一个或多个仲裁器队列,提供对读事务的响应的自动响应机制以及在功能模式之间切换存储​​器控制的切换机制。和自动响应模式。测试控制器将生成测试事务并将测试事务传输到内存控制器。存储器控制器将阻止一个或多个事务仲裁器,将多个测试事务置于一个或多个仲裁器队列中,并在发生事件时取消阻止事务仲裁器。

著录项

  • 公开/公告号US10204025B2

    专利类型

  • 公开/公告日2019-02-12

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号US201715442039

  • 发明设计人 LAKSHMINARAYANA PAPPU;

    申请日2017-02-24

  • 分类号G11C29/00;G06F11/277;G06F13/42;G06F13/38;G06F13/40;G11C29/32;G11C29/38;G06F11/22;G11C29/12;

  • 国家 US

  • 入库时间 2022-08-21 12:13:27

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号