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Methods and apparatus for a vector subsystem for use with a programmable mixed-radix DFT/IDFT processor
Methods and apparatus for a vector subsystem for use with a programmable mixed-radix DFT/IDFT processor
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机译:用于与可编程混合基数DFT / IDFT处理器一起使用的矢量子系统的方法和设备
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摘要
A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input memory addresses are used to shuffle the input data in the memory bank based on a radix factorization associated with an N-point DFT, and the output memory addresses are used to unload the vector data from the memory bank to compute radix factors of the radix factorization.
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