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Heterogeneous integration using wafer-to-wafer stacking with die size adjustment
Heterogeneous integration using wafer-to-wafer stacking with die size adjustment
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机译:使用晶片间调整及晶粒尺寸调整的异质整合
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摘要
A method is provided for three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes that include a first wafer and a second wafer. The method includes manufacturing the second wafer in accordance with a periodicity that matches the periodicity of the first wafer. The method further includes placing, by a laser-based patterning device, a pattern in spaces between dies of the second wafer. The method also includes stacking the first wafer onto the second wafer. The first wafer includes logic circuitry, and the second wafer includes a backside illuminated image sensor.
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