Sample clock source for digital data systems

摘要

A sample clock source includes a master oscillator providing a square wave at a predetermined frequency. A counter and at least one flip-flop are joined to receive the square wave and produce several different output square waves having reduced frequencies. A selector is provided to allow user selection of the different square waves. The selected square wave is provided to a pulse generator which produces a pulse having a known duration at the selected reduced frequency. The pulse generator output can be buffered and provided as the sample clock source. The buffer amplifier is designed to drive long cables with sufficient stability a signal fidelity.