Chapter 50 Direct Digital Synthesizer Based Clock Source for ADC Sampled System

摘要

In this paper a Direct Digital Synthesizer (DDS) clock source application in sampled system is proposed. It is used to replace the analog Phase-Locked Loop (PLL) of a multi-formats test set that supports wireless mobile telecommunication. The DDS in this work operates from 1 μHz to 150 MHz with utilization range of 2.5-40 MHz. The rms jitter is less than 8 ps and peak jitter less than 20 ps for a reference clock signal of 20 MHz. From result, the design achieves phase noise less than -100 dBc/Hz at 1 kHz offset. It also demonstrates a total cost reduction of 61 % as compared to analog PLL implementation.