首页> 外国专利> TIME SLOT DESIGNING DEVICE, TIME SLOT DESIGNING METHOD, AND RECORDING MEDIUM HAVING TIME SLOT DESIGNING PROGRAM STORED THEREON

TIME SLOT DESIGNING DEVICE, TIME SLOT DESIGNING METHOD, AND RECORDING MEDIUM HAVING TIME SLOT DESIGNING PROGRAM STORED THEREON

机译:时隙设计装置,时隙设计方法和记录有该时隙设计程序的介质

摘要

A time slot designing device capable of outputting a correction location and a correction reason of a constraint relating to a slot allocation result that satisfies a corrected constraint is provided. A slot designing device 10 includes an output means 11 for outputting a correction constraint being a constraint as a correction target included in a constraint group relating to a constraint satisfaction problem from which a satisfiable solution is not derived, and a correction reason being a reason why the correction constraint is corrected; and a derivation means 12 for deriving a satisfiable solution of a constraint satisfaction problem generated based on the constraint group in which the output correction constraint is corrected. The derivation means 12 outputs information indicating the correction constraint and the correction reason that are output up until the satisfiable solution is derived.
机译:提供一种时隙设计设备,其能够输出与满足校正后的约束的时隙分配结果有关的约束的校正位置和校正原因。时隙设计装置 10 包括输出装置 11 ,该输出装置 11 用于输出校正约束,该校正约束是作为约束的校正目标的约束,该约束包括在与约束满足问题有关的约束组中。不能得到令人满意的解,并且校正原因是校正约束被校正的原因。推导装置 12 ,用于推导基于其中校正了输出校正约束的约束组而生成的约束满足问题的可满足解。导出装置 12 输出表示直到导出可满足的解为止的校正约束和校正原因的信息。

著录项

  • 公开/公告号US2019149466A1

    专利类型

  • 公开/公告日2019-05-16

    原文格式PDF

  • 申请/专利权人 NEC CORPORATION;

    申请/专利号US201716090623

  • 发明设计人 SATOSHI YAMAZAKI;

    申请日2017-04-10

  • 分类号H04L12/741;H04L12/861;

  • 国家 US

  • 入库时间 2022-08-21 12:09:58

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