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Method for reducing conductor track spacing in electronic circuit boards and electronic circuit board with reduced spacing between conductor tracks

机译:用于减小电子电路板中的导体迹线间距的方法以及具有减小的导体迹线之间的间距的电子电路板

摘要

A method for reducing conductor track spacings in a printed circuit board, wherein the printed circuit board has an input part, wherein the input part is fed by a supply voltage, and has an output part, comprising the following steps: inserting an intermediate conductor track which has an intermediate potential derived from the input part, maintaining a functional insulation gap between the intermediate conductor track and adjacent conductor tracks of the input part, maintaining a safety-relevant insulation gap between the intermediate conductor track and the adjacent conductor tracks of the output part. The intermediate potential has, with respect to adjacent conductor tracks of the output part, a voltage which corresponds at most to the supply voltage of the input part.
机译:一种用于减小印刷电路板中的导体轨道间距的方法,其中,印刷电路板具有输入部分,其中,输入部分由电源电压馈电,并且具有输出部分,包括以下步骤:插入中间导体轨道其具有源自输入部分的中间电势,在输入部分的中间导体轨道和相邻导体轨道之间保持功能绝缘间隙,在输出的中间导体轨道和相邻导体轨道之间保持安全相关的绝缘间隙部分。相对于输出部分的相邻导体迹线,中间电势具有最大对应于输入部分的电源电压的电压。

著录项

  • 公开/公告号US10257922B2

    专利类型

  • 公开/公告日2019-04-09

    原文格式PDF

  • 申请/专利权人 OSRAM GMBH;

    申请/专利号US201615773205

  • 发明设计人 PETER HUMMEL;STEFAN MANNHARDT;

    申请日2016-10-19

  • 分类号H05K7/02;H02H9/04;H05K1/02;F21Y115/10;F21V23/02;

  • 国家 US

  • 入库时间 2022-08-21 12:08:50

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