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Method and System Providing Fourier Transform Based Signal Processing with Reduced Computational Complexity

机译:提供具有降低的计算复杂度的基于傅立叶变换的信号处理的方法和系统

摘要

According to an aspect of the present invention, a signal processor comprises an N-point phase FFT transformer operative to perform a FFT like transformation according to a first relation; <math overflow="scroll"><mrow><mrow><mrow><mi>Y</mi><mo></mo><mrow><mo>[</mo><mi>k</mi><mo>]</mo></mrow></mrow><mo>=</mo><mrow><munderover><mo>∑</mo><mrow><mi>n</mi><mo>=</mo><mn>0</mn></mrow><mrow><mi>n</mi><mo>=</mo><mrow><mi>N</mi><mo>-</mo><mn>1</mn></mrow></mrow></munderover><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mrow><msup><mi>exp</mi><mrow><mo>[</mo><mrow><mi>j</mi><mo></mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo></mo><mrow><mi>angle</mi><mo></mo><mstyle><mspace width="0.8em" height="0.8ex" /></mstyle><mo>[</mo><mrow><mi>x</mi><mo></mo><mrow><mo>(</mo><mi>n</mi><mo>)</mo></mrow></mrow><mo>]</mo></mrow></mrow><mo>]</mo></mrow></msup><mo>*</mo><mrow><mi>exp</mi><mo></mo><mrow><mo>[</mo><mfrac><mrow><mrow><mo>-</mo><mi>j</mi></mrow><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mn>2</mn><mo></mo><mi>π</mi><mo></mo><mstyle><mspace width="0.3em" height="0.3ex" /></mstyle><mo></mo><mi>kn</mi></mrow><mi>N</mi></mfrac><mo>]</mo></mrow></mrow></mrow></mrow></mrow><mo>,</mo></mrow></math> ;wherein angle [x(n)] representing the phase of the signal x(n). In that, a plurality of butterfly units with each butterfly unit in the plurality of butterfly units comprises an adder, subtractor and a multiplier, wherein the adder, the subtractor and multiplier receive a phase only signals with a signal amplitude less than unity. The butterfly units are arranged in plurality of stages to perform the operation as in the first relation.
机译:根据本发明的一个方面,一种信号处理器包括:N点相位FFT变换器,用于根据第一关系执行类似FFT的变换;以及 <![CDATA [<数学溢出=“ scroll”> Y [ k ] = n = 0 n = N - 1 exp [ j angle [ x n ] ] * exp [ - j 2 π kn N ] ]]> ;其中角度[x(n)]表示信号x(n)的相位。其中,具有多个蝶形单元中的每个蝶形单元的多个蝶形单元包括加法器,减法器和乘法器,其中加法器,减法器和乘法器仅接收信号幅度小于1的相位信号。蝶形单元以多级布置以执行第一关系中的操作。

著录项

  • 公开/公告号US2019123944A1

    专利类型

  • 公开/公告日2019-04-25

    原文格式PDF

  • 申请/专利权人 MMRFIC TECHNOLOGY PVT. LTD.;

    申请/专利号US201816163824

  • 发明设计人 GANESAN THIAGARAJAN;

    申请日2018-10-18

  • 分类号H04L27/22;G06F17/14;H04L27/26;

  • 国家 US

  • 入库时间 2022-08-21 12:07:04

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