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INTEGRATED CIRCUIT STRUCTURE INCLUDING DEEP N-WELL SELF-ALIGNED WITH STI AND METHOD OF FORMING SAME

机译:带有STI自对准深N阱的集成电路结构及其形成方法

摘要

The disclosure is directed to integrated circuit (IC) structures, and more particularly, to IC structures including a deep n-well that is self-aligned with a shallow trench isolation (STI). The integrated circuit structure may include: a first pair of isolation regions within a substrate; a first region of the substrate between the first pair of isolation regions having a first conductivity type; a second region of the substrate beneath the first pair of isolation regions and the first region of the substrate having a second conductivity type opposite the first conductivity type of the first region of the substrate, wherein the second region of the substrate includes a second pair of isolation regions that are self-aligned with and in contact with the first pair of isolation regions.
机译:本公开内容针对集成电路(IC)结构,并且更具体地,涉及包括具有与浅沟槽隔离(STI)自对准的深n阱的IC结构。该集成电路结构可以包括:衬底内的第一对隔离区;以及第二对隔离区。在第一对隔离区域之间的具有第一导电类型的衬底的第一区域;在第一对隔离区域下方的衬底的第二区域和衬底的第一区域具有与衬底的第一区域的第一导电类型相反的第二导电类型,其中衬底的第二区域包括第二对隔离区域。与第一对隔离区自对准并与之接触的隔离区。

著录项

  • 公开/公告号US2019088557A1

    专利类型

  • 公开/公告日2019-03-21

    原文格式PDF

  • 申请/专利权人 GLOBALFOUNDRIES INC.;

    申请/专利号US201715705429

  • 发明设计人 JAGAR SINGH;JEROME J. B. CIAVATTI;

    申请日2017-09-15

  • 分类号H01L21/8238;H01L27/092;H01L29/06;H01L29/08;

  • 国家 US

  • 入库时间 2022-08-21 12:06:13

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