COMPUTER PROCESSING UNIT (CPU) ARCHITECTURE FOR CONTROLLED AND LOW POWER SAVE OF CPU DATA TO PERSISTENT MEMORY

摘要

Improvements to computer processing unit (CPU) architecture flush caches to persistent memory (PM) memory devices (e.g., persistent memory in dual in-line memory modules or PM DIMMs) after system power failure and perform specific shutdown of system on chip (SOC) and CPU components to lower auxiliary power cost and obviate CPU processing delays associated with cache flushes to PM memories at synchronization points. CPU architecture improvements comprise separating power lines used by a SOC into parts that can be immediately shutoff upon power failure and parts that receive auxiliary power, and using a power shutdown controller upon system power failure to control terminating auxiliary power to CPU components (e.g., L1, L2 and L3 caches) upon completion of cache flush at each level of CPU memory hierarchy to decrease power consumption by higher powered components as quickly as possible until all data is safely saved on PM memories.