首页> 外国专利> LDPC decoder design to significantly increase throughput in ASIC by utilizing pseudo two port memory structure

LDPC decoder design to significantly increase throughput in ASIC by utilizing pseudo two port memory structure

机译:LDPC解码器设计通过利用伪两端口存储器结构来显着提高ASIC的吞吐量

摘要

A method and apparatus allows single port memory devices to be accessed as pseudo two port memory devices. An access table is created to map the single port memory device to a single port even bank and a single port odd bank. The single port memory device is then accessed based on the mapping. An initial number of entries from the access table are retrieved in order to read addresses in the memory device until a predetermined delay expires. Simultaneous operations are then performed to read from rows in the memory device and write to rows in the memory device. Once all memory addresses have been read, write operations are sequentially performed in rows of the memory device based on the remaining entries of the access table.
机译:一种方法和装置允许将单端口存储设备作为伪两端口存储设备进行访问。创建访问表以将单个端口存储设备映射到单个端口偶数库和单个端口奇数库。然后根据映射访问单端口存储设备。为了访问存储设备中的地址,从访问表中检索出初始数量的条目,直到预定的延迟到期为止。然后执行同时操作以从存储设备中的行读取并写入存储设备中的行。读取完所有内存地址后,将根据访问表的其余条目在存储设备的行中顺序执行写操作。

著录项

  • 公开/公告号US10168938B2

    专利类型

  • 公开/公告日2019-01-01

    原文格式PDF

  • 申请/专利权人 HUGHES NETWORK SYSTEMS. LLC;

    申请/专利号US201615361227

  • 申请日2016-11-25

  • 分类号H03M13/11;G06F3/06;G06F12/06;G11C8/10;G11C7/10;G11C7/22;

  • 国家 US

  • 入库时间 2022-08-21 12:05:07

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