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Methods, systems, and computer program product for a PCI implementation handling multiple packets

机译:用于PCI实现中处理多个数据包的方法,系统和计算机程序产品

摘要

Disclosed are peripheral component interconnect (PCI) implementations and methods for implementing PCI implementations handling posted transaction layer packets (TLPs) and completion TLPs. PCI implementations include one or more receive buffers storing completion TLPs and posted TLPs, a set of write and read pointers for the receive buffers, a token manager to associate ordering tokens with posted TLPs, and a pointer-based ordering mechanism to determine an order for handling posted and completion TLPs. PCI implementations may further include an identification-based ordering mechanism to revise the order. The methods identify a completion TLP and multiple posted TLPs, associate a posted TLP with an ordering token, and determine the order for handling the completion and posted TLPs with at least the pointer-based ordering mechanism. The methods may further optionally revise the order with at least the identification-based ordering mechanism.
机译:公开了外围组件互连(PCI)实现和用于实现PCI实现的方法,该PCI实现处理已发布的事务层数据包(TLP)和完成TLP。 PCI实现包括一个或多个存储完成TLP和已发布TLP的接收缓冲区,用于该接收缓冲区的一组写入和读取指针,将排序令牌与已发布TLP相关联的令牌管理器以及基于指针的排序机制来确定订单的顺序处理已发布和完成的TLP。 PCI实现可以进一步包括基于标识的排序机制以修改该命令。该方法识别完成TLP和多个发布的TLP,将发布的TLP与订购令牌相关联,并至少使用基于指针的排序机制来确定用于处理完成和发布的TLP的顺序。该方法可以进一步可选地至少利用基于识别的排序机制来修改该顺序。

著录项

  • 公开/公告号US10176126B1

    专利类型

  • 公开/公告日2019-01-08

    原文格式PDF

  • 申请/专利权人 CADENCE DESIGN SYSTEMS INC.;

    申请/专利号US201514754508

  • 发明设计人 BIKRAM BANERJEE;ANISH MATHEW;

    申请日2015-06-29

  • 分类号G06F13/00;G06F13/16;G06F13/42;

  • 国家 US

  • 入库时间 2022-08-21 12:04:20

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