SHIFT REGISTER ARCHITECTURE BASED ON INCREMENTAL CYCLIC SHIFTS USED FOR ENCODING/ DECODING OF QC-LDPC CODES

摘要

Aspects of the present disclosure relate to a shift register architecture for quasi-cyclic low-density parity check, QC-LDPC, encoding or decoding performing cyclic shifts corresponding to the parity-check matrix, P-matrix, of a QC-LDPC code, i.e. P-matrix rotations. The P- matrix rotations may be performed by a plurality of shift registers, where each shift register is configured to receive a respective set of bits corresponding to a respective column in the P-matrix. The bits may correspond to information bits to be encoded utilizing QC-LDPC encoding or coded bits to be decoded utilizing QC-LDPC decoding. Each cycle, the shift registers may incrementally rotate (e.g., cyclically shift) their respective sets of bits to achieve a respective individual shift amount corresponding to a number of bit positions. The respective individual shift amount of each shift register may be less than or equal to a maximum shift amount per cycle. In some examples, the maximum shift amount per cycle corresponds to three bit positions.