METHOD AND APPARATUS FOR REDUCING OUTPUT VOLTAGE RIPPLE IN HYSTERETIC BOOST OR BUCK-BOOST CONVERTER

摘要

An apparatus and method for reducing an output voltage ripple of a converter (500) are provided. The apparatus may include a controller (550) for controlling the converter, wherein the controller may include a clock generating circuit (506) that generates a periodic clock signal (CLK) containing periodic clock pulses, and the control circuit that causes the clock generating circuit to asynchronously initiate a clock pulse based on a difference between a feedback voltage (VFB) of the converter and a reference voltage (VREF). The apparatus may also include an on-time modulation circuit which modulates the on-time based on the difference between the reference voltage and the sampled output voltage.