Three-Dimensional Calibration Structures and Methods for Measuring Buried Defects on Three-Dimensional Semiconductor Wafers

摘要

A three-dimensional calibration structure for measuring buried defects on a semiconductor device is disclosed. The three-dimensional calibration structure includes a defect standard wafer (DSW) that includes one or more programmed surface defects. The three-dimensional calibration structure includes a flat layer deposited on the DSW. The three-dimensional calibration structure includes a layer stack deposited on a flat layer. The layer stack includes two or more alternating layers. The three-dimensional calibration structure includes a cap layer deposited on the layer stack. The deposition of the cap layer is followed by one or more air gaps in the layer stack. The three-dimensional calibration structure includes one or more holes formed in at least one of a cap layer, a layer stack, or a flat layer.