Self-testable bus system and use of this self-test capability for assigning bus node addresses with recognition of the interchanging of inputs and outputs

摘要

A data bus system with bus nodes (SL1, SL2, SL2) for a serial data bus is proposed, each having a bus shunt resistor (R2), which is inserted in the data bus in each case. Furthermore, they should have an addressing current source (Iq1, Iq2, Iq2) for determining the bus position of the bus node in the data bus, which can additionally feed an addressing current in the manner regulated in the data bus such that the total current (i1, i2, i3) passes through the bus -Shunt resistor (R2) of the bus node (SI1, SL2, SL3) corresponds to a predetermined or calculated or otherwise determined sum current (I). The control takes place via the said control circuit (R2, D1, D3, F, Iq1, Iq2, Iq3). The addressing current flows through the bus shunt resistor (R2) of the relevant Autoaddressierungsbusknotens. A variant of the proposed bus node has means (R2, D1) to detect the current through the bus shunt resistor (R2), which may include the acquisition of a measured value. This detected current through the bus shunt resistor (R2) may be used for a self-test such that the above-described failures (e.g., bus shunt resumption) can be detected. In a particularly preferred variant of the auto-addressing bus node, the addressing current source (Iq1, Iq2, Iq2) increases the addressing current with a first time constant (τ) and decrements it with a second time constant (τ) which is smaller than the first time constant (τ).