Device and method for horizontal vector addition of signed / unsigned words and double words

摘要

An apparatus and method for performing a packed horizontal addition of words and double words. An embodiment of a processor includes, for example: a decoder for decoding a packed horizontal add instruction to generate a decoded packed horizontal add instruction, the packaged horizontal add instruction including opcode and operands identifying a plurality of packed words; a source register for storing a first plurality of packed words; an execution circuit for executing the decoded instruction, the execution circuit comprising: an operand selection circuit for identifying a first and second packed word from the source register according to the operand and the opcode of the packed horizontal addition instruction; an adder circuit for adding the first and second packed words to produce a temporary sum; a temporary memory of at least 17 bits for storing the temporary sum; a saturation circuit for saturating the temporary sum, if necessary, to produce a final resu a destination register for storing the final result as a packed result word at a designated data element position.