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MASK-INTEGRATED SURFACE PROTECTION TAPE

机译:面膜综合保护胶带

摘要

{Technical problem} To provide a mask-integrated surface protective tape for a plasma dicing method, which has a good protection property of the patterned surface of the semiconductor wafer in the backgrinding step which is performed in a large thinning degree and a good peeling property of the mask material layer from a base film of the surface protective tape, and which is low in adhesive deposits and occurrence of defective chips. Further, to provide a photolithography process-unnecessary mask-integrated surface protective tape.{Solution to problem} A mask-integrated surface protective tape that can be used for production of semiconductor chips, with the production containing the following steps (a) to (d), which tape comprises a base film and a mask material layer provided on the base film, wherein a wetting tension of the base film on the side from which the mask material layer has been peeled is 20.0 mN/m or more and 48.0 mN/m or less, and wherein a surface roughness Ra of the base film on the side from which the mask material layer has been peeled is within a range of 0.05 µm or more and 2.0 µm or less when measured in conformity to JIS B0601, [Steps (a) to (d)](a) a step of, in the state of having laminated the mask-integrated surface protective tape on the side of a patterned surface of a semiconductor wafer, grinding the backing-face side of the semiconductor wafer; laminating a wafer fixing tape on the backing-face side of the ground semiconductor wafer; and supporting and fixing the wafer to a ring flame;(b) a step of, after peeling the base film of the mask-integrated surface protective tape, thereby to expose the mask material layer on top, forming an opening of a street of the semiconductor wafer by cutting a portion of the mask material layer corresponding to the street of the semiconductor wafer by laser;(c) a plasma-dicing step of segmentalizing the semiconductor wafer on the street by a SFplasma, thereby singulating the semiconductor wafer into semiconductor chips; and(d) an ashing step of removing the mask material layer by an Oplasma.
机译:{技术问题}提供一种用于等离子体切割的掩模一体的表面保护带,其在以大的薄化度进行的背面研磨步骤中对半导体晶片的图案化表面具有良好的保护性并且剥离性良好。从表面保护带的基膜上除去掩膜材料层的粘合剂层,其粘合剂沉积和缺陷芯片的发生率低。此外,提供不需要光刻工艺的集成有掩模的表面保护带。{问题的解决方案}一种集成有掩模的表面保护带,其可用于半导体芯片的生产,所述生产包含以下步骤(a)至( d)带,其包括基膜和设置在该基膜上的掩模材料层,其中,在已剥离掩模材料层的一侧上的基膜的润湿张力为20.0mN / m以上且48.0mN。 / m以下,并且其中当根据JIS B0601进行测量时,在剥离了掩模材料层的一侧上的基膜的表面粗糙度Ra在0.05μm以上且2.0μm以下的范围内,步骤(a)至(d)](a)的步骤是,在将掩模集成表面保护带层压在半导体晶片的图案化表面侧的状态下,研磨半导体的背面侧。晶圆在被研磨的半导体晶片的背面侧层叠晶片固定带。将晶片支撑并固定在环形火焰上;(b)在剥离集成有掩模的表面保护带的基膜之后,露出顶部的掩模材料层,从而形成晶片的街道的开口的步骤。通过激光切割掩模材料层中与半导体晶片的走线相对应的部分来形成半导体晶片;(c)通过SFplasma分割在街道上的半导体晶片的等离子体切割步骤,从而将半导体晶片分割成半导体芯片; (d)灰化步骤,通过Oplasma去除掩模材料层。

著录项

  • 公开/公告号EP3506334A4

    专利类型

  • 公开/公告日2020-08-19

    原文格式PDF

  • 申请/专利权人 FURUKAWA ELECTRIC CO. LTD.;

    申请/专利号EP20170846396

  • 发明设计人 GOTO YUSUKE;YOKOI HIROTOKI;

    申请日2017-08-28

  • 分类号H01L21/78;C09J201;H01L21/308;H01L21/683;

  • 国家 EP

  • 入库时间 2022-08-21 11:42:11

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