DRAM ARCHITECTURE TO REDUCE ROW ACTIVATION CIRCUITRY POWER AND PERIPHERAL LEAKAGE AND RELATED METHODS

摘要

A semiconductor device may include a plurality of memory cells, and at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice. The superlattice may includea plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first power switching device configured to couple theat least one peripheral circuit to a first voltage supply during a first operating mode, and a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a second operating mode.