METHOD FOR SCALABLE PARALLEL-COMPUTING OF DESIGN RULE CHECKING (DRC)

摘要

Processing time of design rule checking (DRC) is identified as one of the most pressing bottlenecks during the design of circuits implemented in modern fabrication technologies that prescribe complex contextual rules for manufacturability.;To address this issue, a method is disclosed that relies on space-partitioning the circuit, thus obtaining a tree-based geometrical representation of the circuit. Operations between geometries encapsulated in nodes belonging to one or multiple trees are shown to be well-suited for parallel processing.;Disclosed are practical techniques that implement such operations on processors with parallel computing capabilities.;Disclosed is an improved DRC method for implementing parallel processing of computing operations by effectively decoupling dependencies between different sequences of computing operations. In a more generic way, this approach may be used to implement parallel processing of time-consuming electronic design automation operations.;A novel DRC method is disclosed that leverages the powerful computing capabilities of current GPUs (Graphic Processor Units). It is shown that, by space-partitioning the circuit, the DRC computation method can be described as a highly parallel formulation which benefits from the GPU parallel computing power. The invention relies on two level of parallelization. Firstly, multiple rules can be executed independently on multiple GPUs. Secondly, each rule is split into many independent simpler tasks that are executed in parallel on the same GPU. This is possible due to the hierarchical representation of the circuit.;It is shown that leveraging parallel computing techniques greatly improves DRC execution times opening the road for real-time execution of DRC on GPUs. Indeed, in one embodiment the GPU implementation of a minimum-distance rule outperforms its single-processor counterpart by two orders of magnitude, achieving real-time design rule checking. Furthermore, the proposed algorithm is scalable to multiple GPUs, can handle multi-billion transistor devices and can accommodate all kind of manufacturing rules needed by the industry.