INTER-PROCESSOR COMMUNICATION METHOD FOR ACCESS LATENCY BETWEEN SYSTEM-IN-PACKAGE (SIP) DIES

摘要

A system and method wherein die-to-die communication are provided between a first die (102) and a second die (103) contained in a common integrated circuit (IC) package (101), a first processor (105) on the first die communicatively coupled to the first connectivity circuitry (108) by the first processor bus (111) and configured to provide first bus transactions (402), to be provided to the second connectivity circuitry, to the first processor bus, the first connectivity circuitry configured to utilize a multiple simultaneous outstanding transaction capability supporting multiple simultaneous outstanding write transactions concurrent with multiple simultaneous outstanding read transactions (404), the second connectivity circuitry configured to provide processor bus flow control information and elasticity buffer status information pertaining to the elasticity buffer to the first connectivity circuitry via a common message for flow control (408).