首页> 外国专利> Manufacturing methods for low temperature poly-silicon array substrate and low temperature poly-silicon thin-film transistor

Manufacturing methods for low temperature poly-silicon array substrate and low temperature poly-silicon thin-film transistor

机译:低温多晶硅阵列基板及低温多晶硅薄膜晶体管的制造方法

摘要

Manufacturing methods for a low temperature poly-silicon array substrate and for a low temperature poly-silicon thin-film transistor are provided. The manufacturing method for the low temperature poly-silicon array substrate includes: providing a substrate; forming a poly-silicon semiconductor pattern on the substrate; a first channel region, a first source region and a first drain region being formed on a first portion of the poly-silicon semiconductor pattern that corresponds to the first thin-film transistor and a second thin-film transistor; forming a gate insulation layer; performing an activation treatment; forming a gate on the gate insulation layer after the activation treatment; forming an interlayer insulation layer between the gate insulation layer and the gate; performing a hydrogen treatment; forming a source/drain pattern on the interlayer insulation layer after the hydrogen treatment, and connecting the source/drain pattern to the source region and the drain region in the poly-silicon semiconductor pattern via a through hole.
机译:提供了一种低温多晶硅阵列基板和低温多晶硅薄膜晶体管的制造方法。该低温多晶硅阵列基板的制造方法包括:提供基板;以及在基板上形成多晶硅半导体图案;在多晶硅半导体图案的与第一薄膜晶体管和第二薄膜晶体管对应的第一部分上形成第一沟道区,第一源极区和第一漏极区;形成栅极绝缘层;进行活化治疗;活化处理后,在栅极绝缘层上形成栅极。在栅极绝缘层和栅极之间形成层间绝缘层;进行氢处理;在氢处理之后在层间绝缘层上形成源极/漏极图案,并且经由通孔将源极/漏极图案连接到多晶硅半导体图案中的源极区和漏极区。

著录项

  • 公开/公告号US10658402B2

    专利类型

  • 公开/公告日2020-05-19

    原文格式PDF

  • 申请/专利号US201715737131

  • 发明设计人 CHEN CHEN;

    申请日2017-09-21

  • 分类号H01L27/12;H01L21/77;H01L29/66;H01L29/786;

  • 国家 US

  • 入库时间 2022-08-21 11:30:30

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号