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System, method, and computer program product for handling combinational loops associated with the formal verification of an electronic circuit design
System, method, and computer program product for handling combinational loops associated with the formal verification of an electronic circuit design
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机译:用于处理与电子电路设计的形式验证有关的组合回路的系统,方法和计算机程序产品
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摘要
The present disclosure relates to a method for electronic circuit design. Embodiments may include providing, using at least one processor, an electronic design and isolating a combinational loop associated with the electronic design. Embodiments may further include inserting a sequential element in a loop path of the combinational loop, wherein the sequential element has a clock that is at least twice as fast as a fastest system clock associated with the electronic design. Embodiments may also include generating a property that determines whether an input and an output of the sequential element is never different and determining whether the property is true using formal verification.
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