首页>
外国专利>
Semiconductor package with reduced parasitic coupling effects and process for making the same
Semiconductor package with reduced parasitic coupling effects and process for making the same
展开▼
机译:具有减小的寄生耦合效应的半导体封装及其制造工艺
展开▼
页面导航
摘要
著录项
相似文献
摘要
The present disclosure relates to a semiconductor package with reduced parasitic coupling effects, and a process for making the same. The disclosed semiconductor package includes a thinned flip-chip die and a first mold compound component with a dielectric constant no more than 7. The thinned flip-chip die includes a back-end-of-line (BEOL) layer with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, a device layer over the upper surface of the BEOL layer, and a buried oxide (BOX) layer over the device layer. The BEOL layer includes a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion. Herein, the first mold compound component extends through the BOX layer and the device layer to the first surface portion.
展开▼