Phase-continuous reference clock frequency shift for digital phase locked loop

摘要

Systems, circuitries, and methods are described for phase-continuous shifting of a reference clock frequency from f_REF to N_REF for a DPLL that includes a DCO and a feedback loop that generates a feedback signal. The DPLL generates a local oscillator signal based on an analog reference signal having a reference clock frequency f_REF and a digital reference signal having the reference clock frequency f_REF. In one example, the method includes receiving a target time and at expiration of a first nonzero interval after the target time, generating a subsequent feedback signal having the target reference clock frequency Nf_REF; at expiration of a second nonzero interval after the target time, generating a subsequent analog reference signal having the target reference clock frequency Nf_REF; and at expiration of a third nonzero interval after the target time, generating a subsequent digital reference clock signal having the target reference clock frequency Nf_REF.