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Reduced noise dynamic comparator for a successive approximation register analog-to-digital converter
Reduced noise dynamic comparator for a successive approximation register analog-to-digital converter
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机译:用于逐次逼近寄存器模数转换器的降低噪声的动态比较器
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摘要
A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.
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